Rangeen Basu Roy Chowdhury

Intel Corporation

I am CPU Architect at Intel Corporation and my team is part of Intel's Platform Engineering Group. We architect and design Intel's big cores that go in to products such as i3, i5, i7, Xeons.

I graduated with a PhD in Computer Engineering from North Carolina State University in 2016. I was part of the Center for Efficient & Scalable Computing group at NCSU. My research interests include power efficient computing with a strong focus on efficient microprocessor design. I was advised by Prof. Eric Rotenberg.


Resume:

Curriculum Vitae in PDF
Resume in PDF
Google Scholar

Email:

rbasuro [AT] ncsu [DOT] edu
rangeen [DOT] basu [AT] gmail [DOT] com

Contact Address:

3600 Juliette Lane
Santa Clara, CA-95054
U.S.A

Home

Research

Adaptive Microprocessors



An adaptive microprocessor dynamically adapts its resources to the charateristics of the workload that is running on it. This allows mor optimum performance per watt i.e. it gets the best possible performance with the least possible energy, sometimes trading off energy savings for performance degradation. My research involves studying the overheads of an adaptive CPU over non-adaptive ones and trying to come up with clever microarchitectural techniques to minimize the overheads.

Architectural Power Modelling


In this era of deep sub-micron technologies, desiging porcessors for power efficiencies have become extremely crucial. Historically, power consumption was not a huge concern and so, measurements were done after first silicon comes back from the fab. This approach is not suiatble anymore and architects and designers must accurately understand power consumption of a design. We are looking for ways to estimate power consumtion of a design during archtectural exploration i.e. using a performance simulator, but with a fidelity that approaches an RTL based power estimation flow.

Heterogeneous Multicore



A slightly different but equally effective paradigm of signle ISA adaptiveity is that of "Single ISA Heterogenous CMPs". As opposed to dynamically adapting resources in a single CPU, heterogeneous multicores deal with varying charateristics of workload by migrating the workload to a core which is tuned for it. A single program might be migrated back and forth between many different cores to achieve the optimum performance per watt. Selecting the core types at design time is a research question. Even if the right cores are available, migrating a thread back and forth are fraught obvious overheads. We are looking at innovative ways such as 3D stacking to minimize the overheads of migration.

Publications

Peer Reviewed Conferences


V. Srinivasan, R. Basu Roy Chowdhury, E. Forbes, R. Widialaksono, Z. Zhang, J. Schabel, S. Ku, S. Lipa, E. Rotenberg, W. R. Davis, and P. Franzon. H3 (Heterogeneity in 3D): A Logic-on-logic 3D-stacked Heterogeneous Multi-core Processor Nov 5-8, 2017. [pdf]


S. Ku, E. Forbes, R. Basu Roy Chowdhury, and E. Rotenberg. A Case for Standard-Cell Based RAMs in Highly-Ported Superscalar Processor Structures. (ISQED-17) March 2017. [pdf]


R. Widialaksono, R. Basu Roy Chowdhury, Z. Zhang, J. Schabel, S. Lipa, E. Rotenberg, W. R. Davis, and P. Franzon. Physical Design of a 3D-stacked Heterogeneous Multi-Core Processor (3DIC-2016) Nov 8-11, 2016. [pdf] [slides]


R. Basu Roy Chowdhury, A. Kannepalli, S. Ku, and E. Rotenberg. Anycore: A Synthesizable RTL Model for Exploring and Fabricating Adaptive Superscalar Cores. (ISPASS-17) April 2016. [pdf] [slides]


E. Rotenberg, B. H. Dwiel, E. Forbes, Z. Zhang, R. Widialaksono, R. Basu Roy Chowdhury, N. Tshibangu, S. Lipa, W. R. Davis, and P. D. Franzon. Rationale for a 3D Heterogeneous Multi-core Processor. Proceedings of the 31st IEEE International Conference on Computer Design (ICCD-31), pp. 154-168, October 2013. [pdf]


J. RoyChoudhury, T. P. Banerjee, A. Nathvani, R. Basu Roy Chowdhury, and A. K. Bhattacharya. Design methodology internal sub state observer using CPLD. In Nature & Biologically Inspired Computing, 2009. NaBIC 2009. pp. 1636-1640. IEEE, 2009. [pdf]


Workshop Papers

E. Forbes, R. Chowdhury, B. Dwiel, A. Kannepalli, V. Srinivasan, Z. Zhang, R. Widialaksono, T. Belanger, S. Lipa, E. Rotenberg, W. Davis, and P. Franzon. Experience with Two FabScalar-Based Chips. 6th Workshop on Architectural Research Prototyping (WARP'15), in conjunction with ISCA-42, June 2015. [pdf]


R. Basu Roy Chowdhury, A. Kannepalli,and E. Rotenberg. FabScalar-RISCV. 2nd RISC-V Workshop. Berkeley, CA, June 2015. [abstract] [slides] [video]


Posters

R. Basu Roy Chowdhury, A. Kannepalli, and E. Rotenberg. AnyCore-1: A Comprehensively Adaptive 4-way Superscalar Core. Poster session of Hot Chips 2016, August 21-23, 2016.[abstract] [poster]


S. Ku, E. Forbes, R. Basu Roy Chowdhury, and E. Rotenberg. A Case for Standard-Cell Based RAMs in Highly-Ported Superscalar Processor Structures. Poster session of the 2016 Design Automation Conference (DAC'16), June 7, 2016. [pdf]


E. Forbes, Z. Zhang, R. Widialaksono, B. Dwiel, R. Basu Roy Chowdhury, V. Srinivasan, S. Lipa, E. Rotenberg, W. R. Davis, and P. D. Franzon. Under 100-cycle Thread Migration Latency in a Single-ISA Heterogeneous Multi-core Processor. Poster session of Hot Chips 2015, August 23-25, 2015. [pdf]


Course Projects and Term Papers from NCSU

R. Basu Roy Chowdhury. A case for cache core decoupling in CPMs - ECE 706: Advanced Parallel Architecture (Prof. Greg Byrd), Fall 2015. [pdf]


R. Basu Roy Chowdhury, S. Sharma.Virtualizing GPUs for CUDA based HPC applications - ECE 792: Data Center Architecture (Prof. Greg Byrd & Prof. Yannis Viniotis), Spring 2014. [pdf]


R. Basu Roy Chowdhury. Analysis of different FinFET design techniques used for Low-Power Robust SRAMs - ECE 733: Advanced Digital Electronics (Prof. Paul Franzon), Spring 2014. [pdf]


R. Basu Roy Chowdhury, D. Howe.Implementing Aggressive Branch Prediction in FabScalar - ECE 721: Advanced Microarchitecture (Prof. Eric Rotenberg), Fall 2012. [pdf]


R. Basu Roy Chowdhury.Implementing Profile Driven Global Code Motion in LLVM - ECE 566: Code Generation and Optimization (Prof. James Tuck), Fall 2012. [pdf]


K.k Shenoy, Jayaganeshwar N. , R. Basu Roy Chowdhury.A 5.5 GHz Network on Chip in 45nm CMOS Process - ECE 546: VLSI System Design (Prof. Rhett Davis) Fall 2011. [pdf]



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