Vinesh Srinivasan

Ph.D Student, Graduate Research Assistant
Department of Electrical and Computer Engineering
North Carolina State University

Address

Department of Electrical and Computer Engineering
Box 7911
NC State University
Raleigh, NC 27695-7911
USA

Contact

Email : vsriniv3(at)ncsu(dot)edu
Phone : +1 9194804445

Introduction

I am a PhD student specializing in Computer Engineering at North Carolina State University. I work under the guidance of Dr.Eric Rotenberg. My research interests are computer architecture mainly focussing on microarchitecture. I finished my MS-thesis in the summer of 2015 from NCSU before pursuing my PhD. Prior to masters, I was part of the High Performance Computing (HPC) group at Waran Research Foundation (WARFT).

Publications

  • H3 (Heterogeneity in 3D): A Logic-on-logic 3D-stacked Heterogeneous Multi-core Processor
    V. Srinivasan, R. Basu Roy Chowdhury, E. Forbes, R. Widialaksono, Z. Zhang, J. Schabel, S. Ku, S. Lipa, E. Rotenberg, W. R. Davis, and P.D. Franzon.
    35th IEEE International Conference on Computer Design (ICCD-35) Nov 5-8, 2017. [pdf]

  • Experiences with Two FabScalar-based Chips
    E. Forbes, R. Basu Roy Chowdhury, B. Dwiel, A. Kannepalli, V. Srinivasan, Z. Zhang, R. Widialaksono, T. Belanger, S. Lipa, E. Rotenberg, W. R. Davis, and P. D. Franzon.
    6th Workshop on Architectural Research Prototyping (WARP'15), in conjunction with ISCA-42, June 14, 2015. [pdf]

  • Performance and Energy Efficient Cache System Design: Simultaneous Execution of Multiple Applications on Heterogeneous Cores
    Venkateswaran Nagarajan, Vinesh Srinivasan et.al
    IEEE Computer Society Annual Symposium on VLSI, ISVLSI 2013, Natal Brazil. [pdf]

  • Compilation Accelerator on Silicon
    Venkateswaran Nagarajan, Vinesh Srinivasan et.al
    IEEE Computer Society Annual Symposium on VLSI, ISVLSI 2012, University of Massachusetts, Amherst. [pdf]

  • SCOC IP Cores for Custom Built Supercomputing Nodes
    Venkateswaran Nagarajan, Vinesh Srinivasan et.al
    IEEE International Symposium on VLSI, ISVLSI 2012, University of Massachusetts, Amherst. [pdf]

Posters

  • Under 100-cycle Thread Migration Latency in a Single-ISA Heterogeneous Multi-core Processor
    E. Forbes, Z. Zhang, R. Widialaksono, B. Dwiel, R. Basu Roy Chowdhury, V. Srinivasan, S. Lipa, E. Rotenberg, W. R. Davis, and P. D. Franzon.
    Poster session of Hot Chips 2015, August 23-25, 2015.[pdf]

  • WIMAC - A Novel Many core simulator for very large clusters running multiple applications
    Venkateswaran Nagarajan, Vinesh Srinivasan et.al
    Poster at International supercomputing conference ISC 2012, Hamburg, Germany. [pdf]

MS Thesis

Phase II Implementation and Verification of the H3 Processor M.S. Thesis, Department of Electrical and Computer Engineering, North Carolina State University, August 2015.[link]